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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998 mos integrated circuit m m m m pd16682 1/65 duty lcd controller/driver with on-chip ram data sheet document no. s13368ej3v0ds00(3rd edition) date published march 2000 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd16682 is a lcd controller/driver that includes enough ram capacity to drive full-dot lcd. each chip can drive a full-dot lcd consisting of up to 132 x 65 dots. this chip is suitable for cellular phones, japanese or chinese-language pagers, and other devices that display japanese or chinese characters using either 16 x 16 or 12 x 12 dots per character. features lcd controller/driver with on-chip display ram able to operate using +3-v single power supply on-chip booster circuit: switchable between 3x and 4x modes ram for dot displays: 132 x 65 bits outputs : 132 segments, 65 commons serial or 8-bit parallel data inputs (switchable between 80 series and 68 series mpus) on-chip divider resistor selectable bias settings (can be set as 1/9 bias or 1/7 bias) on-chip oscillation circuit ordering information part number package m pd16682w-xxx note wafer m pd16682p-xxx note chip m pd16682n-xxx note -051 standard tcp (output olb: 0.15-mm pitch), for evaluation note the following four temperature gradients can be selected. -001: C0.05 % / c -002: C0.1 % / c -003: C0.15 % / c -004: 0 % / c remark purchasing the above chip/wafer entails exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative. ?
data sheet s13368ej3v0ds00 2 m m m m pd16682 1. block diagram p,/s v rs /cs1 cs2 /rd(e) /wr(r,/w) d 7 (si) c 1 , c 1 i/o buffer timing generator c 2 + , c c 3 , c 3 v dd2 dc/dc converter d/a converter op amp v r v lc1 v lc2 v lc3 v lc4 v lc5 hpm command decoder address decoder data register display data ram 132 x 65 bits lcd voltage generator 132 bits latch 65 bits register common driver segment driver com 0 com 63 coms seg 0 seg 131 132 132 v lcd v ss v dd a0 frs fr d 5 d 0 /dof test out /res d 6 (scl) cl m,/s irs to + - 2 - + - c86 cls v dd ' v ss ' test1 to test3 test4 to test5 remark /xxx indicates active low si gnals. ?
data sheet s13368ej3v0ds00 3 m m m m pd16682 2. pin configuration (pad layout) chip size: 2.66 mm x 9.84 mm 254 255 289 1 85 86 120 121 x y
data sheet s13368ej3v0ds00 4 m m m m pd16682 table 2 - - - - 1. pad layout (1/3) pad no. pad name x [ m m] y [ m m] pad type pad no. pad name x [ m m] y [ m m] pad type 1 dummy1 C3804 C1198 c 59 v lc2 1448 C1198 b 2 frs C3682 C1198 b 60 v lc2 1538 C1198 b 3 fr C3592 C1198 b 61 v lc3 1628 C1198 b 4 cl C3502 C1198 b 62 v lc3 1718 C1198 b 5 /dof C3412 C1198 b 63 v lc4 1808 C1198 b 6 test out C3322 C1198 b 64 v lc4 1898 C1198 b 7v ss C3232 C1198 b 65 v lc5 1988 C1198 b 8 /cs1 C3142 C1198 b 66 v lc5 2078 C1198 b 9 cs2 C3052 C1198 b 67 v ss 2168 C1198 b 10 v dd C2962 C1198 b 68 v ss 2258 C1198 b 11 /res C2872 C1198 b 69 test1 2348 C1198 b 12 a0 C2782 C1198 b 70 test2 2438 C1198 b 13 v ss C2692 C1198 b 71 test3 2528 C1198 b 14 /wr(r,/w) C2602 C1198 b 72 test4 2618 C1198 b 15 /rd(e) C2512 C1198 b 73 test5 2708 C1198 b 16 v dd C2422 C1198 b 74 v dd 2798 C1198 b 17 d 0 C2332 C1198 b 75 m,/s 2888 C1198 b 18 d 1 C2242 C1198 b 76 cls 2978 C1198 b 19 d 2 C2152 C1198 b 77 v ss 3068 C1198 b 20 d 3 C2062 C1198 b 78 c86 3158 C1198 b 21 d 4 C1972 C1198 b 79 p,/s 3248 C1198 b 22 d 5 C1882 C1198 b 80 v dd 3338 C1198 b 23 d 6 (scl) C1792 C1198 b 81 hpm 3428 C1198 b 24 d 7 (si) C1702 C1198 b 82 v ss 3518 C1198 b 25 v dd C1612 C1198 b 83 irs 3608 C1198 b 26 v dd C1522 C1198 b 84 v dd 3698 C1198 b 27 v dd C1432 C1198 b 85 dummy2 3820 C1198 c 28 v dd2 C1342 C1198 b 86 dummy3 4788 C1032 c 29 v dd2 C1252 C1198 b 87 com 31 4788 C940 a 30 v dd2 C1162 C1198 b 88 com 30 4788 C880 a 31 v dd2 C1072 C1198 b 89 com 29 4788 C820 a 32 v lcd C982 C1198 b 90 com 28 4788 C760 a 33 v lcd C892 C1198 b 91 com 27 4788 C700 a 34 v lcd C802 C1198 b 92 com 26 4788 C640 a 35 v ss C712 C1198 b 93 com 25 4788 C580 a 36 v ss C622 C1198 b 94 com 24 4788 C520 a 37 v ss C532 C1198 b 95 com 23 4788 C460 a 38 c 1 + C442 C1198 b 96 com 22 4788 C400 a 39 c 1 + C352 C1198 b 97 com 21 4788 C340 a 40 c 1 C C262 C1198 b 98 com 20 4788 C280 a 41 c 1 C C172 C1198 b 99 com 19 4788 C220 a 42 c 2 + C82 C1198 b 100 com 18 4788 C160 a 43 c 2 + 8 C1198 b 101 com 17 4788 C100 a 44 c 2 C 98 C1198 b 102 com 16 4788 C40 a 45 c 2 C 188 C1198 b 103 com 15 4788 20 a 46 c 3 + 278 C1198 b 104 com 14 4788 80 a 47 c 3 + 368 C1198 b 105 com 13 4788 140 a 48 c 3 C 458 C1198 b 106 com 12 4788 200 a 49 c 3 C 548 C1198 b 107 com 11 4788 260 a 50 v ss 638 C1198 b 108 com 10 4788 320 a 51 v dd 728 C1198 b 109 com 9 4788 380 a 52 v dd 818 C1198 b 110 com 8 4788 440 a 53 v rs 908 C1198 b 111 com 7 4788 500 a 54 v rs 998 C1198 b 112 com 6 4788 560 a 55 v r 1088 C1198 b 113 com 5 4788 620 a 56 v r 1178 C1198 b 114 com 4 4788 680 a 57 v lc1 1268 C1198 b 115 com 3 4788 740 a 58 v lc1 1358 C1198 b 116 com 2 4788 800 a
data sheet s13368ej3v0ds00 5 m m m m pd16682 table 2 - - - - 1. pad layout (2/3) pad no. pad name x [ m m] y [ m m] pad type pad no. pad name x [ m m] y [ m m] pad type 117 com 1 4788 860 a 175 seg 53 750 1198 a 118 com 0 4788 920 a 176 seg 54 690 1198 a 119 coms 4788 980 a 177 seg 55 630 1198 a 120 dummy4 4788 1073 c 178 seg 56 570 1198 a 121 dummy5 4023 1198 c 179 seg 57 510 1198 a 122 seg 0 3930 1198 a 180 seg 58 450 1198 a 123 seg 1 3870 1198 a 181 seg 59 390 1198 a 124 seg 2 3810 1198 a 182 seg 60 330 1198 a 125 seg 3 3750 1198 a 183 seg 61 270 1198 a 126 seg 4 3690 1198 a 184 seg 62 210 1198 a 127 seg 5 3630 1198 a 185 seg 63 150 1198 a 128 seg 6 3570 1198 a 186 seg 64 90 1198 a 129 seg 7 3510 1198 a 187 seg 65 30 1198 a 130 seg 8 3450 1198 a 188 seg 66 C30 1198 a 131 seg 9 3390 1198 a 189 seg 67 C90 1198 a 132 seg 10 3330 1198 a 190 seg 68 C150 1198 a 133 seg 11 3270 1198 a 191 seg 69 C210 1198 a 134 seg 12 3210 1198 a 192 seg 70 C270 1198 a 135 seg 13 3150 1198 a 193 seg 71 C330 1198 a 136 seg 14 3090 1198 a 194 seg 72 C390 1198 a 137 seg 15 3030 1198 a 195 seg 73 C450 1198 a 138 seg 16 2970 1198 a 196 seg 74 C510 1198 a 139 seg 17 2910 1198 a 197 seg 75 C570 1198 a 140 seg 18 2850 1198 a 198 seg 76 C630 1198 a 141 seg 19 2790 1198 a 199 seg 77 C690 1198 a 142 seg 20 2730 1198 a 200 seg 78 C750 1198 a 143 seg 21 2670 1198 a 201 seg 79 C810 1198 a 144 seg 22 2610 1198 a 202 seg 80 C870 1198 a 145 seg 23 2550 1198 a 203 seg 81 C930 1198 a 146 seg 24 2490 1198 a 204 seg 82 C990 1198 a 147 seg 25 2430 1198 a 205 seg 83 C1050 1198 a 148 seg 26 2370 1198 a 206 seg 84 C1110 1198 a 149 seg 27 2310 1198 a 207 seg 85 C1170 1198 a 150 seg 28 2250 1198 a 208 seg 86 C1230 1198 a 151 seg 29 2190 1198 a 209 seg 87 C1290 1198 a 152 seg 30 2130 1198 a 210 seg 88 C1350 1198 a 153 seg 31 2070 1198 a 211 seg 89 C1410 1198 a 154 seg 32 2010 1198 a 212 seg 90 C1470 1198 a 155 seg 33 1950 1198 a 213 seg 91 C1530 1198 a 156 seg 34 1890 1198 a 214 seg 92 C1590 1198 a 157 seg 35 1830 1198 a 215 seg 93 C1650 1198 a 158 seg 36 1770 1198 a 216 seg 94 C1710 1198 a 159 seg 37 1710 1198 a 217 seg 95 C1770 1198 a 160 seg 38 1650 1198 a 218 seg 96 C1830 1198 a 161 seg 39 1590 1198 a 219 seg 97 C1890 1198 a 162 seg 40 1530 1198 a 220 seg 98 C1950 1198 a 163 seg 41 1470 1198 a 221 seg 99 C2010 1198 a 164 seg 42 1410 1198 a 222 seg 100 C2070 1198 a 165 seg 43 1350 1198 a 223 seg 101 C2130 1198 a 166 seg 44 1290 1198 a 224 seg 102 C2190 1198 a 167 seg 45 1230 1198 a 225 seg 103 C2250 1198 a 168 seg 46 1170 1198 a 226 seg 104 C2310 1198 a 169 seg 47 1110 1198 a 227 seg 105 C2370 1198 a 170 seg 48 1050 1198 a 228 seg 106 C2430 1198 a 171 seg 49 990 1198 a 229 seg 107 C2490 1198 a 172 seg 50 930 1198 a 230 seg 108 C2550 1198 a 173 seg 51 870 1198 a 231 seg 109 C2610 1198 a 174 seg 52 810 1198 a 232 seg 110 C2670 1198 a
data sheet s13368ej3v0ds00 6 m m m m pd16682 table 2 - - - - 1. pad layout (3/3) pad no. pad name x [ m m] y [ m m] pad type 233 seg 111 C2730 1198 a 234 seg 112 C2790 1198 a 235 seg 113 C2850 1198 a 236 seg 114 C2910 1198 a 237 seg 115 C2970 1198 a 238 seg 116 C3030 1198 a 239 seg 117 C3090 1198 a 240 seg 118 C3150 1198 a 241 seg 119 C3210 1198 a 242 seg 120 C3270 1198 a 243 seg 121 C3330 1198 a 244 seg 122 C3390 1198 a 245 seg 123 C3450 1198 a 246 seg 124 C3510 1198 a 247 seg 125 C3570 1198 a 248 seg 126 C3630 1198 a 249 seg 127 C3690 1198 a 250 seg 128 C3750 1198 a 251 seg 129 C3810 1198 a 252 seg 130 C3870 1198 a 253 seg 131 C3930 1198 a 254 dummy6 C4022 1198 c 255 dummy7 C4788 1032 c 256 com 32 C4788 940 a 257 com 33 C4788 880 a 258 com 34 C4788 820 a 259 com 35 C4788 760 a 260 com 36 C4788 700 a 261 com 37 C4788 640 a 262 com 38 C4788 580 a 263 com 39 C4788 520 a 264 com 40 C4788 460 a 265 com 41 C4788 400 a 266 com 42 C4788 340 a 267 com 43 C4788 280 a 268 com 44 C4788 220 a 269 com 45 C4788 160 a 270 com 46 C4788 100 a 271 com 47 C4788 40 a 272 com 48 C4788 C20 a 273 com 49 C4788 C80 a 274 com 50 C4788 C140 a 275 com 51 C4788 C200 a 276 com 52 C4788 C260 a 277 com 53 C4788 C320 a 278 com 54 C4788 C380 a 279 com 55 C4788 C440 a 280 com 56 C4788 C500 a 281 com 57 C4788 C560 a 282 com 58 C4788 C620 a 283 com 59 C4788 C680 a 284 com 60 C4788 C740 a 285 com 61 C4788 C800 a 286 com 62 C4788 C860 a 287 com 63 C4788 C920 a 288 coms C4788 C980 a 289 dummy8 C4788 C1073 c remark pad type a: pad size(al): 47 x 105 m m 2 (typ.) pad size (through hole): 20 x 72 m m 2 (typ.) bump size: 35 x 92.5 m m 2 (typ.) bump height: 17 m m(typ.) pad type b: pad size(al): 75 x 105 m m 2 (typ.) pad size (through hole): 42 x 72 m m 2 (typ.) bump size: 67 x 92.5 m m 2 (typ.) bump height: 17 m m(typ.) pad type c: pad size(al): 118 x 105 m m 2 (typ.) pad size (through hole): 85 x 72 m m 2 (typ.) bump size: 110 x 92.5 m m 2 (typ.) bump height: 17 m m(typ.)
data sheet s13368ej3v0ds00 7 m m m m pd16682 3. pin descriptions 3.1 power supply system pins pin symbol pin name pad no. i/o function description v dd logic power supply pins 25 to 27 power supply pins for logic. apply the logic power supply voltage from an external source. v dd2 booster circuit power supply pins 28 to 31 power supply pins for booster circuit. apply the booster circuit power supply voltage from an external source. v ss logic/driver ground pins 35 to 37 ground pins for logic and driver circuit. connect these pins to an external ground. v lcd driver power supply pins 32 to 34 power supply pins for driver. output pins for internal booster circuit. connect a 1- m f capacitor for boosting between these pins and the gnd pins. if not using the internal booster circuit, a direct driver power supply can be input. v dd power supply pins for fixed mode pins 10,16,51, 52,74,80, 84 these power supply pins are used to set the mode pins as fixed. v ss ground pins for fixed mode pins 7,13,50, 67,68,77, 82 these ground pins are used to set the mode pins as fixed. v lc1 to v lc5 reference power supply pins for driver 57 to 66 these are reference power supply pins for the lcd driver. connect a smoothing capacitor if an internal bias has been selected. c 1 + , c 1 - c 2 + , c 2 - c 3 + , c 3 - capacitor connection pins 38 to 49 these are capacitor connection pins for the booster circuit. connect a 1- m f capacitor.
data sheet s13368ej3v0ds00 8 m m m m pd16682 3.2 logic system pins (1/2) pin symbol pin name pad no. i/o function description p,/s select data input 79 input this pin is used to select between parallel data input and serial data input. p,/s = h : parallel data input p,/s = l : serial data input this setting cannot be switched after power-on. for details, see 5. description of functions . /cs1,cs2 chip select 8,9 input these pins are used for the chip select signal. when /cs1 = l and cs2 = h, this signal is active and can be used for i/o of data and commands. /rd(e) read (enable) 15 input when connected to 80 series mpu : active low this pin connects the 80 series mpus rd signal. data bus output status is set when this signal is low. when connected to 68 series mpu : active high it is used as the enable clock input pin for the 68 series mpu. /wr(r,/w) write (read/write) 14 input when connected to 80 series mpu: active low this pin connects the 80 series mpu's /wr signal. signals on the data bus are latched at the rising edge of the /wr signal. when connected to 68 series mpu this pin is an input pin for read/write control signals. r,/w = h : read r,/w = l : write c86 interface select 78 input this pin is used to select the mpu interface. c86 = h : 68 series mpu interface c86 = l : 80 series mpu interface d 0 to d 5 data bus 17 to 22 input /output when used with a parallel interface, these pins correspond to data bus bits d 0 to d 5 . when used with a serial interface, they are pulled down internally. d 6 (scl) data bus/serial clock 23 input /output when used with a parallel interface, this pin corresponds to data bus bit d 6 . when used with a serial interface, it is a serial clock input pin. d 7 (si) data bus/serial data input 24 input /output when used with a parallel interface, this pin corresponds to data bus bit d 7 . when used with a serial interface, it is a serial data input pin. a0 data command 12 input this pin is connected to the lsb in the ordinary mpu address bus to distinguish between data and commands. a0 = h : indicates that display data exists in bits d 0 to d 7 . a0 = l : indicates that display control commands exist in bits d 0 to d 7 . test out test output 6 output this pin is used as a test output. leave this pin open when used for this purpose. /res reset 11 input this pin is used to perform an internal reset when at low level. clk clock select 76 input this pin is used to select the valid/invalid setting for the display clocks on-chip oscillation circuit. cls = h : on-chip oscillation circuit is valid cls = l : on-chip oscillation circuit is invalid (external input) when cls = l, a display clock is input via the cl pin.
data sheet s13368ej3v0ds00 9 m m m m pd16682 3.2 logic system pins (2/2) pin symbol pin name pad no. i/o function description fr frame signal 3 input /output this pin is used as an i/o pin for the lcds ac conversion signal. this pin is used (along with the frs pin) for the static drive. frs static signal 2 output this pin is used as an output pin for the static drive. this pin is used (along with the fr pin) for the static drive. this pin is used to select master or slave operation mode. timing signals required for the lcd are output during master mode and are input during slave mode to ensure synchronization of the lcd block. m,/s = h: master operation mode m,/s = l: slave operation mode note the settings below, based on the status of the m,/s and cls pins. m,/s cls oscillation circuit power supply circuit cl fr frs /dof hh valid valid output output output output l invalid valid input output output output lh invalid invalid input input hi-z input m,/s master/slave 75 input l invalid invalid input input hi-z input this pin is used as the display clock i/o pin. note the settings below, based on the status of the m,/s and cls pins. m,/s cls cl hh output l input lh input l input cl display clock input 4 input /output when using this pin in master or slave mode, connect it to the corresponding cl pin. /dof blink control 5 input /output this pin is used to control blinking in the lcd. m,/s = h : output m,/s = l : input when using this pin in master or slave mode, connect it to the corresponding /dof pin. hpm power supply circuit select pin for lcd driver 81 input this pin is used as a power control pin of the power supply circuit for the lcd driver. hpm = h : normal mode hpm = l : high-power mode irs select pin for v lc1 regulating resistor 83 input this pin is used to select the resistor that is used to regulate the v lc1 voltage. irs = h : select on-chip resistor irs = l : do not select on-chip resistor. the v lc1 voltage is regulated via the v r pin and an external divided resistor. use of the on-chip resistor cannot be selected or deselected via a hard reset or via a reset command. instead, use this pin to select the setting. test1 to test3 test pins 69 to 71 input these are test pins for ic tests. normally, these pins should be left open. test4,test5 test pins 72,73 output these are test pins for ic tests. normally, these pins should be left open.
data sheet s13368ej3v0ds00 10 m m m m pd16682 3.3 driver system pins pin symbol pin name pad no. i/o function description seg 0 to seg 131 segment 122 to 253 output segment output pins com 0 to com 63 common 87 to 118, 256 to 287 output common output pins coms indicator common 288 output common output pins for indicator the same signal is output from pin 2. v rs op amp inputs 53,54 input these are input pins for the op amp that regulates the lcd driver voltage. leave the v rs pin open when using the on-chip power supply. v r 55,56 when not using the on-chip power supply, a reference voltage v reg must be input. when using an external power supply, connect the v r pin to a resistor used to regulate the lcd voltage. dummy1 to dummy5 dummy pins 1,85,86, 120,121 since these pins are not connected to any internal circuits, they should be left open when they are not being used.
data sheet s13368ej3v0ds00 11 m m m m pd16682 4. pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. pin name i/o recommended connection of unused pins notes p,/s input mode setting pin 1 /cs1 input connect to v ss cs2 input connect to v dd /rd(e) input connect to v dd (80 series interface), connect to v dd or v ss (serial interface) /wr (r,/w) input connect to v dd or v ss (serial interface) c86 input mode setting pin 1 d 0 to d 5 input/output leave open (when using serial interface) 4 d 6 (scl) input/output d 7 (si) input/output a0 input data/command setting pin 2 test out output leave open /res input connect to v dd cls input mode setting pin 1 fr input/output leave open (when using master mode, m,/s = h) frs output leave open /dof input/output leave open (when using master mode, m,/s = h) m,/s input mode setting pin 1 cl input/output display clock 3 hpm input mode setting pin 1 irs input mode setting pin 1 test1 input leave open 4 test2 input leave open 4 test3 input leave open 4 test4 output leave open test5 output leave open notes 1. connect to v dd or v ss according to the selected mode. 2. input microcontroller output from v dd or v ss according to the selected register. 3. this pin is an output when m,/s = h and cls = h but should otherwise be used to input the display clock. 4. these pins are pulled down to v ss in the ic.
data sheet s13368ej3v0ds00 12 m m m m pd16682 5. description of functions 5.1 mpu interface 5.1.1 select interface type the m pd16682 transfers data either via an 8-bit bidirectional data bus (d 7 to d 0 ) or via a serial data input (si). the p,/s pin can be set to either high or low levels to select 8-bit parallel data input or serial data input, as shown in the table below. p,/s /cs1 cs2 a0 /rd /wr c86 d 7 d 6 d 5 - d 0 h: parallel input /cs1 cs2 a0 /rd /wr c86 d 7 d 6 d 5 -d 0 l: serial input /cs1 cs2 a0 note 1 note 1 note1 si scl note2 notes 1. fix this pin as either h or l. 2. high impedance 5.1.2 parallel interface if the parallel interface has been selected (p,/s = h), setting the c86 pin either high or low determines whether to connect directly to the 80 series mpu or the 68 series mpu, as shown in the table below. p,/s /cs1 cs2 a0 /rd d 7 - d 0 h: 68 series mpu bus /cs1 cs2 a0 e d 7 - d 0 l: 80 series mpu bus /cs1 cs2 a0 /rd d 7 - d 0 the data bus signal can be identified according to the combination of a0, /rd(e), and /wr (r,/w) signals, as shown in the table below. common 68 series 80 series function a0 r,/w /rd /wr h h l h read display data h l h l write display data l h l h read status l l h l write control data (command)
data sheet s13368ej3v0ds00 13 m m m m pd16682 (1) 80 series parallel interface when 80 series parallel data transfer has been selected, data is written to the m pd16682 at the rising edge of the /wr signal. the data is output to the data bus when the /rd signal is l. figure 5 - - - - 1. 80 series interface data bus status /cs1 (cs2=h) /wr /rd dbn hi-z hi-z data write data read valid data (2) 68 series parallel interface when 68 series parallel data transfer has been selected, data is written at the falling edge of the e signal when the r,/w signal is l. during the data read operation, the data bus enters the output status when the r,/w signal is h, outputs valid data at the rising edge of the e signal, and enters the high-impedance state at the falling edge of the r,/w signal (r,/w = l) figure 5 - - - - 2. 68 series interface data bus status /cs1 (cs2=h) r,/w e dbn hi-z hi-z hi-z invalid data valid data
data sheet s13368ej3v0ds00 14 m m m m pd16682 5.1.3 serial interface if the serial interface has been selected (p,/s = l) and if the chip is in the active state (/cs1 = l and cs2 = h), both serial data input (si) and serial clock input (scl) can be received. the serial interface includes an 8-bit shift register and a 3-bit counter. serial data is captured at the rising edge of the serial clock and is clocked in via the serial data input pins in sequence from d 7 to d 0 . at the rising edge of the eighth serial clock, data is converted to 8-bit parallel data. input via the a0 pin can be used to determine whether the input serial data is display data or a command (display data when a0 = h, command when a0 = l). the timing for reading and identifying input via a0 occurs at the rising edge of the eighth x n serial clock once the chips status is active. a serial interface signal chart is shown below. figure 5 - - - - 3. serial interface chart d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 123456789101112131415161718 /cs1 si scl a0 cs2 remarks1. when the chips status is inactive, the shift register and counter are both reset to their initial values. 2. data cannot be read when using the serial interface. 3. for the scl signal, caution is advised concerning the wires terminating reflection and noise from external sources. we recommend to check the operation on the actual equipment. 5.1.4 chip select the m pd16682 has two chip select pins (/cs1 and cs2). the mpu interface or serial interface can be used only when /cs1 = l and cs2 = h. when the chip select pin is inactive, d 7 to d 0 are set to high impedance (invalid) and input of a0, /rd, or /wr is invalid. if the serial interface has been selected, the shift register and counter are both reset. 5.1.5 display data ram and internal register access access to the m pd16682 from the mpu supports high-speed data transfers since the cycle time (t cyc ) is met and there is no need for wait time. when data transfer occurs between the m pd16682 and the mpu, the data is held in a bus holder belonging to the internal data bus and is written to the display data ram before the next data write cycle. when the mpu reads the contents of the display data ram, the data read during the first data read cycle (dummy cycle) is first held in the bus holder and is read from the bus holder to the system bus during the next data read cycle. note with caution that, due to constraints on the read sequence for the display data ram, when the address is set, the data is not output from the address specified by the next read command but rather is output to the address specified during the second data read operation. consequently, one dummy read operation is strictly required after setting an address or after a write cycle. figure 5 - 4 illustrates this situation.
data sheet s13368ej3v0ds00 15 m m m m pd16682 figure 5 - - - - 4. write and read operations n n n n+1 preset n increment n+1 n+2 /rd data read signal /wr n n n+1 n+2 bus holder address preset column address address set #n dummy read data read #n data read #n+1 mpu n n+1 n+2 n+3 n n+1 n+2 n+3 /wr data bus holder write signal latch mpu writing internal timing reading internal timing
data sheet s13368ej3v0ds00 16 m m m m pd16682 6. display data ram 6.1 display data ram this is the ram that is used to store the displays dot data. the ram configuration is 65 (8 pages x 8 bits + 1) x 132 bits. any specified bit can be accessed by selecting the corresponding page address and column address. as is shown in figure 6 - 1 below, the display data (d 7 to d 0 ) from the mpu corresponds to the common direction in the lcd, so that if a multiple set of m pd16682 chips is used, there are fewer constraints on transfers of display data and relatively more freedom for display configurations. the mpu accesses the display data ram for read/write operations via the i/o buffer, and these operations are independent of the lcd driver signal read operations. therefore, there are absolutely no adverse effects (such as flicker) in the display when display data ram is accessed asynchronously in relation to the lcd contents. figure 6 - - - - 1. lcd data and lcd display lcd data lcd display d 0 0111 0 com 0 d 1 1000 0 com 1 d 2 0000 0 com 2 d 3 0111 0 com 3 d 4 1000 0 com 4 ... ... 6.2 page address circuit the page address set command specifies the page address in the display data ram, as is shown in figure 6 - 2. to access a different page, simply specify a different page address using this command. page address 8 (d 3 ,d 2 ,d 1 ,d 0 = 1,0,0,0) is a ram area that is used exclusively for indicator, so only display data d 0 is valid. 6.3 column address circuit the column address set command specifies the column address in the display data ram, as is shown in figure 6 - 2. the specified column address is incremented each time a display data read or write command is input, so the mpu is able to successively access display data. incrementation of the column address stops at 83h. the column address and page address are mutually independent, which means that to switch from column 83h on page 0 to column 00h on page 1, both the page address and column address must be separately specified again. also, as is shown in table 6 - 1, the adc command (segment driver direction select command) can be used to invert the correspondence between the display data rams column address and segment output. this reduces the number of ic layout constraints that are imposed when setting up the lcd module. table 6 - - - - 1. relation between display data ram column address and segment output seg output seg 0 seg 131 adc 0 00h ? column address ? 83h (d 0 ) 1 83h ? column address ? 00h
data sheet s13368ej3v0ds00 17 m m m m pd16682 6.4 line address circuit as is shown in figure 6 - 2, the line address circuit specifies the line address that corresponds to a com output for displaying the contents of display data ram. the display start line address set command usually specifies the highest line in the display (corresponding to the com 0 output when in normal mode or the com 63 output when in inverted mode). thus, there are 65 lines in the direction of incrementation of line address starting from the specified display start line address. the screen can be scrolled by dynamically changing the line address via the display start line address set command. figure 6 - - - - 2. specification of display start line address in display data ram line com d 3 d 2 d 1 d 0 address output d 0 00h com 0 d 1 01h com 1 d 2 02h com 2 0000d 3 03h com 3 d 4 04h com 4 d 5 05h com 5 d 6 06h com 6 d 7 07h com 7 d 0 08h com 8 d 1 09h com 9 d 2 0ah com 10 0001d 3 page1 d 4 0ch com 12 d 5 0dh com 13 d 6 0eh com 14 d 7 0fh com 15 d 0 10h com 16 d 1 11h com 17 d 2 12h com 18 0 0 1 0 d 3 d 4 14h com 20 d 5 15h com 21 d 6 16h com 22 d 7 17h com 23 d 0 18h com 24 d 1 19h com 25 d 2 1ah com 26 0011d 3 d 4 1ch com 28 d 5 1dh start com 29 d 6 1eh com 30 d 7 1fh com 31 d 0 20h com 32 d 1 21h com 33 d 2 22h com 34 0100d 3 d 4 24h com 36 d 5 25h com 37 d 6 26h com 38 d 7 27h com 39 d 0 28h com 40 d 1 29h com 41 d 2 2ah com 42 0101d 3 d 4 2ch com 44 d 5 2dh com 45 d 6 2eh com 46 d 7 2fh com 47 d 0 30h com 48 d 1 31h com 49 d 2 32h com 50 0 1 1 0 d 3 d 4 34h com 52 d 5 35h com 53 d 6 36h com 54 d 7 37h com 55 d 0 38h com 56 d 1 39h com 57 d 2 3ah com 58 0111d 3 d 4 3ch com 60 d 5 3dh com 61 d 6 3eh com 62 d 7 3fh com 63 1000d 0 coms 00 01 02 03 04 05 06 07 7c 7d 7e 7f 80 81 82 83 0 d 0 83 82 81 80 7f 7e 7d 7c 07 06 05 04 03 02 01 00 1 d 0 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 124 seg 125 seg 126 seg 127 seg 128 seg 129 seg 130 seg 131 lcd out page address data column adc address page0 page2 page3 page4 page5 page6 page7 page8 0bh 13h 1bh 23h 2bh 33h 3bh com 11 com 19 com 27 com 35 com 43 com 51 com 59 common output status : normal mode note note coms accesses the 65th line regardless of the display start line address.
data sheet s13368ej3v0ds00 18 m m m m pd16682 6.5 display data latch circuit the display data latch circuit is used for temporary storage of display data that has been output to the lcd driver circuit from the display data ram. the commands that are used to set normal/inverted display modes, display on/off status, and display all on/off status are commands that control data in this latch so that there is no modification of the data in the display data ram. 7. oscillation circuit this is a cr-type oscillation circuit that generates the display clock. the oscillation circuit is valid only when cls = h. when cls = l, oscillation is stopped and the display clock is input via the cl pin. 8. display timing generator the display timing generator generates timing signals from the display clock to the line address circuit and the display data latch circuit. display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver output pins. reading of the display data is completely independent of the mpus accessing of the display data ram. consequently, there are no adverse effects (such as flicker) on the lcd panel even when the display data ram is accessed asynchronously in relation to the lcd contents. the internal common timing and lcds ac conversion signal (fr) are both generated from the display clock. as is shown in figure 8 - 1, a drive waveform based on the two-frame ac drive method is generated for the lcd driver circuit. if a multiple set of m pd16682 chips is used, the display timing signals (fr, cl, and /dof) for the slave side must be supplied from the master side. operation mode fr cl /dof master (m,/s = h) on-chip oscillation circuit is valid (cls = h) output output output on-chip oscillation circuit is invalid (cls = l) output input output slave (m,/s = l) on-chip oscillation circuit is invalid (cls = h) input input input on-chip oscillation circuit is invalid (cls = l) input input input
data sheet s13368ej3v0ds00 19 m m m m pd16682 figure 8 - - - - 1. drive waveform when using two-frame ac drive method 12345678 636465 12345678 636465 v lc1 v lc2 v lc3 v lc4 v lc5 v ss seg 1 v lc1 v lc2 v lc3 v lc4 v lc5 v ss com 1 v lc1 v lc2 v lc3 v lc4 v lc5 v ss com 0 v lc1 v lc2 v lc3 v lc4 v lc5 v ss coms ram data fr cl 1frame
data sheet s13368ej3v0ds00 20 m m m m pd16682 9. common output status select circuit with the m pd16682, the common output status select command can be used to set the scan direction for com outputs (see table 9 - 1). as a result, there are fewer ic layout constraints when setting up the lcd module. table 9 - - - - 1. setting of scan direction for com outputs status com scan direction normal (forward) com 0 ? com 63 inverted (reverse) com 63 ? com 0 10. power supply circuit 10.1 power supply circuit the power supply circuit, which supplies the voltage needed to drive the lcd, includes a booster circuit, voltage regulator circuit, and voltage follower circuit. the power control set command is used to control the on/off status of the power supply circuits booster circuit, voltage regulator circuit (v regulator circuit), and voltage follower circuit (v/f circuit). this makes it possible to jointly use an external power supply along with certain functions of the on-chip power supply. table 10 - 1 shows the function that controls the 3-bit data in the power control set command and table 10 - 2 shows a reference chart of combinations. table 10 - - - - 1. control values set to bits in power control set command item status hl d 2 booster circuit control bit on off d 1 voltage regulator circuit control bit on off d 0 voltage follower circuit control bit on off table 10 - - - - 2. reference chart of combinations use status d 2 d 1 d 0 booster circuit v regulator circuit v/f circuit external power supply input booster- related pin <1> use on-chip power supply hhh {{{ v dd2 used <2> use v regulator circuit and v/f circuit only lhh {{ v lcd open <3> use v/f circuit only l l h { v lc1 open <4> use external power supply only lll v lc1 to v lc5 open remarks 1. the booster-related pins are indicated as pins c 1 + , c 1 C , c 2 + , c 2 C , c 3 + , and c 3 C . 2. although combinations other than those shown above are possible, they have no practical uses and therefore cannot be recommended.
data sheet s13368ej3v0ds00 21 m m m m pd16682 10.2 booster circuit 3x and 4x booster circuits have been incorporated in chip to generate the current driving the lcd. when using the internal power supply, connect the booster-related capacitor between c 1 + and c 1 C , c 2 + and c 2 C , and c 3 + and c 3 C . also, connect the level stabilization-related capacitor between v lcd and v ss and set d 2 high to boost the potential between v dd2 and v ss from 3 to 4 times. since the booster circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. the relation between the boosted voltage and the potential is described below. the c 1 + , c 1 C , c 2 + , c 2 C , c 3 + , c 3 C , and v dd2 pins all relate to the booster circuit, so the wire impedance should be minimized. figure 10 - - - - 1. 3x and 4x booster circuits v dd2 = 3 v v ss = 0 v v lcd = 3v dd2 = 9 v (during 3x boost mode) v lcd = 4v dd2 = 12 v (during 4x boost mode) caution when set to 3x boost mode, connect booster-related capacitors between c 2 C and c 3 + and between c 1 + and c 1 C . 10.3 voltage regulator circuit the boost voltage that was generated at v lcd is output via the voltage regulator circuit as the lcd drive voltage v lc1 . since the m pd16682 has a 64-level electronic volume function and an on-chip resistor for v lc1 voltage regulation, various components can be used to configure a highly accurate voltage regulator circuit. 10.3.1 use of on-chip resistor for v lc1 voltage regulation the on-chip resistor for v lc1 voltage regulation and the electronic volume function can be used to regulate the darkness of the lcd contents, not only by adding an external resistor but also by controlling the lcd drive voltage v lc1 by using commands only. the v lc1 voltage can be determined using equation 10 - 1 as within the range of v lc1 < v lcd .
data sheet s13368ej3v0ds00 22 m m m m pd16682 equation 10 - - - - 1. ev 1 lc v ) ra rb 1 ( v + = the equation for determining v ev varies according to the product code (temperature gradient). reg ev v ) 162 1 ( 203 162 v a - = (-001 code, C0.05 % / c) reg ev v ) 162 1 ( 178 162 v a - = (-002 code, C0.1 % / c) reg ev v ) 162 1 ( 221 162 v a - = (-003 code, C0.15 % / c) reg ev v ) 162 1 ( v a - = (-004 code, 0 % / c) ra rb v lc1 + C v ev (constant voltage source + electronic volume) v reg is the ics internal constant voltage source, whose voltage values (at t a = 25 c) are listed in table 10 - 3 below. table 10 - - - - 3. v reg product code temperature gradient (%/ c) v reg (v) -001 C0.05 2.08 -002 C0.1 1.84 -003 C0.15 1.62 -004 0 2.39 given a as the electronic volume command value, when data is set to the 6-bit electronic volume register, one of 64 statuses is set. values for a corresponding to various electronic volume register settings are listed in table 10 - 4 below. table 10 - - - - 4. a a a a values determined by electronic volume register settings d 5 d 4 d 3 d 2 d 1 d 0 a 00000063 00000162 00001161 00001160 ::::::: 1111012 1111101 1111110
data sheet s13368ej3v0ds00 23 m m m m pd16682 rb/ra is an on-chip resistance factor used for the v lc1 voltage regulator. this factor can be controlled among eight levels using the v lc1 voltage regulator resistance factor set command. table 10 - 5 lists reference values for (1+rb/ra) which are set when 3-bit data is set to the v lc1 voltage regulator resistance factor register. table 10 - - - - 5. reference values for (1 + rb/ra) register reference value d 3 d 2 d 1 000 3.5 001 4.0 010 4.5 011 5.0 100 5.5 101 6.0 110 6.5 111 7.0 10.3.2 when using external resistor (not using on-chip resistor for v lc1 voltage regulator) instead of using the on-chip resistor for the v lc1 voltage regulator (irs pin = l), resistors (ra and rb) can be added between v ss and v r and between v r and v lc1 to set the lcd power supply voltage v lc1 . in such cases, the electronic volume function can be used to control the lcd power supply voltage v lc1 using commands to regulate the darkness of the lcd contents. the v lc1 voltage can be determined using equation 10 - 2 as within the range of v lc1 < v lcd . equation 10 - - - - 2. ev 1 lc v ) ' ra ' rb 1 ( v + = the equation for determining v ev varies according to the product code (temperature gradient). reg ev v ) 162 1 ( 203 162 v a - = (-001 code, C0.05 % / c) reg ev v ) 162 1 ( 178 162 v a - = (-002 code, C0.1 % / c) reg ev v ) 162 1 ( 221 162 v a - = (-003 code, C0.15 % / c) reg ev v ) 162 1 ( v a - = (-004 code, 0 % / c) ra' rb' v lc1 + C v lc1 v r v ev (constant voltage source + electronic volume)
data sheet s13368ej3v0ds00 24 m m m m pd16682 10.4 op amp control for level power supply the m pd16682s on-chip power supply circuit is designed for low power consumption (hpm = h). consequently, display quality may be diminished when a large lcd device or panel is used. in such cases, the display quality can be improved by setting hpm = l (high-power mode). we recommend that you check the actual display quality before deciding whether or not to use high-power mode. if setting high-power mode still does not sufficiently improve the display quality, the lcd drivers power supply must be provided from an external source. 10.5 command sequence for stepping down on-chip power supply as shown in the following command sequence, we recommend that you set low power mode and turn off the power before stepping down the on-chip power supply. step description command address (command, status) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 step1 display off 10101110power save command step2 display all on 10100101 (com pound) end on-chip power supply off
data sheet s13368ej3v0ds00 25 m m m m pd16682 10.6 use example of power supply circuit v dd v lcd c 1 c 1 c 2 c 2 c 3 c 3 v ss v lc5 v lc4 v lc3 v lc2 v lc1 v r v rs v dd2 c 4 c 1 c 2 c 3 v lcd c 3 open v ss c 4 c 1 + + + + c 2 c 2 c 3 open c 2 c 1 c 1 + + + + + + + + + - + - + - - + + - - + irs hpm open open a) 4x boost (normal mode/using on-chip power supply) b) 3x boost to logic system power supply to booster circuit power supply note leave the c 2 + and c 3 C pins open. remark c 1 = c 2 = c 3 = c 4 = 1.0 m f
data sheet s13368ej3v0ds00 26 m m m m pd16682 11. reset circuit in the m pd16682, when the /res input is at low level, a reset is executed. the reset (default) settings are described below. 1. display off 2. normal display direction 3. adc select: normal direction (adc command d 0 =l) 4. power control register: (d 2 ,d 1 ,d 0 ) = (0,0,0) 5. data cleared from register in serial interface 6. lcd power supply bias: 1/9 bias 7. read modify write off 8. power save canceled 9. seg/com output: v ss 10. static indicator off static indicator register: (d 2 ,d 1 ) = (0,0) 11. display start line: set to line 1 12. column address: set to address 0 13. page address: set to page 0 14. common output status: normal 15. canceled mode set for on-chip resistance factor for v lc1 voltage regulator v lc1 voltage regulator resistance factor register (d 2 ,d 1 ,d 0 ) = (0,0,0) 16. canceled mode set for electronic volume register electronic volume register: (d 5 ,d 4 ,d 3 ,d 2 ,d 1 ,d 0 ) = (1,0,0,0,0,0) 17. test mode canceled 18. display all off (display all on/off command, d 0 = l) only items 1, 7, and 9 to 18 above are executed when a reset command is used.
data sheet s13368ej3v0ds00 27 m m m m pd16682 12. commands the m pd16682 uses a combination of a0, /rd(e), and /wr(r,/w) to identify data bus signals. command interpretation and execution is performed using internal timing that does not depend on any external clock. the 80 series mpu interface activates commands using low pulse input to the /rd pin during read and activates commands using low pulse input to the /wr pin during write. the 68 series mpu interface sets read mode using high-level input to the r,/w pin and sets write mode using low-level input to the r,/w pin. the command is activated using high pulse input to the e pin. thus, the 68 series mpu interface differs from the 80 series mpu interface in that /rd(e) is at high level during status read and display data read operations, as is shown in the command descriptions and command table. command descriptions using an 80 series mpu interface are shown below. if the serial interface has been selected, data is input sequentially starting from d 7 . 12.1 display on/off this command specifies the displays on/off status. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 0 1 0 10101111 display on 0 display off executing the display all on command while the display is off sets power save (low power) mode. for details, see 12.20 power save (compound command) . when the display is off, output via all driver outputs (segment and common) is at v ss level. 12.2 display start line set this command specifies the address of the display start line in the display data ram, as was shown in figure 6 - 2. the display area extends from the specified line address in the direction of higher line addresses, and includes the number of lines that corresponds to the display duty setting. the display can be smoothly scrolled vertically by using this command to dynamically modify the specified line addresses. for details, see 6.4 line address circuit . a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 line address 0 1 0 01000000 0 000001 1 000010 2 111110 62 111111 63
data sheet s13368ej3v0ds00 28 m m m m pd16682 12.3 page address set this command specifies the page address corresponding to the row address when accessing the display data ram from the mpu side, as was shown in figure 6 - 2. the specified bit in display data ram can be accessed by selecting the corresponding page address and column address. if the page address is changed, the display mode does not change. for details, see 6.2 page address circuit . a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 page address 0 1 0 10110000 0 0001 1 0010 2 0111 7 1000 8 12.4 column address set this command specifies the column address in display data ram, as was shown in figure 6 - 2. the column address is set in a (basically continuous) series of two specifications, one for the high-order four bits and another for the low-order four bits. the column address is automatically incremented (+1) each time the display data ram is accessed, so the mpu is able to continuously read or write display data. incrementation of the column address stops at 83h. at that point the page address can no longer be continuously modified. for details, see 6.3 column address circuit . a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 a7 a6 a5 a4 0 a3a2a1a0 a7 a6 a5 a4 a3 a2 a1 a0 column address 00000000 0 00000001 1 00000010 2 10000010 130 10000011 131
data sheet s13368ej3v0ds00 29 m m m m pd16682 12.5 status read a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 adc on/off reset 0 0 0 0 adc this indicates the relation between the column address and the segment driver. 0: inverted (column address 131Cn ? segn) 1: normal (column address n ? segn) on/off on/off: indicates the displays on/off status. 0: display on 1: display off (this is the opposite of the display on/off command's polarity.) reset this indicates whether or not the system is undergoing a reset via the /res signal or the reset command. 0: operating mode 1: reset in progress 12.6 display data write this command writes 8 bits of data to the specified address in display data ram. after this data has been written, the column address is automatically incremented (+1), which enables the mpu to continuously write display data. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data 12.7 display data read this command reads 8 bits of data from the specified address in display data ram. after this data has been read, the column address is automatically incremented (+1), which enables the mpu to continuously read several words of data. a single dummy read operation is required immediately after the column address has been set. for details, see 5.1.5 display data ram and internal register access . note that the display data cannot be read when using a serial interface. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data
data sheet s13368ej3v0ds00 30 m m m m pd16682 12.8 adc select (segment driver direction select) this command inverts the relation between the display data rams column address and segment driver output, as was shown in figure 6 - 2. consequently, the segment driver output pin number can be inverted by this command. for details, see 6.3 column address circuit. incrementation (+1) of the column address when display data is either written or read is performed according to the column address shown in figure 6 - 2. this command should be input during initialization. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 0 1 0 10110000normal (forward direction) 1 inverted (reverse direction) 12.9 display normal/inverted this command can be used to invert the display on/off control without replacing any of the display data ram contents. the display data ram contents are retained when this command is executed. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 0 1 0 10100110ram data: h lcd on potential (normal) 1 ram data: l lcd on potential (inverted) 12.10 display all on/off this command can be used to set the display all on status forcibly regardless of the display data ram contents. the display data ram contents are retained when this command is executed. this command takes priority over the display normal/inverted command. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 0 1 0 10100100normal display mode 1 display all on 12.11 lcd bias set this command selects the bias setting of the voltage required to drive the lcd. this command is valid when the power supply circuits v/f circuit is operating. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 0 1 0 101000101/9 bias 1 1/7 bias
data sheet s13368ej3v0ds00 31 m m m m pd16682 12.12 read modify write this command is used in a pair with the end command. when this command has been input, the column address is not changed by the display data read command and can be incremented (+1) only by the display data write command. this status is retained until an end command is input. once an end command has been input, the column address returns to the address that was used when the read modify write command was input. this function can be used to lighten the burden on the mpu when repeatedly modifying data in special display areas such as the blinking cursor. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 11100000 caution the commands other than the display data read/write commands can be used even during read modify write mode. however, the column address set command cannot be used. figure 12 - - - - 1. sequence for cursor display no ye s page address set column address set read modify write dummy read data read data write changes completed? end data processing
data sheet s13368ej3v0ds00 32 m m m m pd16682 12.13 end this command is used to cancel read modify write mode and return to the address that was used during column address mode reset. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 11101110 figure 12 - - - - 2. end n n+1 n+2 n+3 n+m n return end read modify write mode set column address 12.14 reset this command initializes the contents of the various command registers. the display data ram is not affected. for details, see 11. reset circuit . the reset operation is performed after the reset command has been input. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 11100010 the reset that occurs when the power supply is applied is performed by issuing a reset signal to the /res pin. it cannot be used as a substitute for the reset command. 12.15 common output status select this command can be used to select the scan direction for the com output pins. for details, see 9. common output status select circuit. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 0 1 0 11000xxxnormal (forward) 1 inverted (reverse) remark x: don't care status selected status normal (forward) com 0 ? com 63 inverted (reverse) com 63 ? com 0
data sheet s13368ej3v0ds00 33 m m m m pd16682 12.16 power control set this command is used to set the function of the power supply circuit. for further description, see 10. power supply circuit. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 selected status 0 1 0 001010xxbooster circuit: off 1 x x booster circuit: on x 0 x v regurator circuit:off x 1 x v regurator circuit: on x x 0 v/f circuit: off x x 1 v/f circuit: on remark x: dont care 12.17 set on-chip resistance factor for v lc1 voltage regulator this command is used to set the on-chip resistance factor for the v lc1 voltage regulator. for details, see 10.3 voltage regulator circuit. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (1+rb/ra) 0 1 0 00100000 3.5 001 4.0 010 4.5 011 5.0 100 5.5 101 6.0 110 6.5 111 7.0 12.18 electronic volume (two-byte command) this command can be used to control the lcd drive voltage v lc1 (which is output from the on-chip lcd power supplys voltage regulator circuit) to regulate the darkness of the lcd contents. this command is a two-byte command that is used in a pair with the electronic volume mode set command and the electronic volume register set command, so be sure to use both commands consecutively. 12.18.1 electronic volume mode set command (first byte) once this command is input, the electronic volume register set command becomes valid. and once the electronic volume mode has been set, any command other than the electronic volume register set command cannot be used. this restriction is cleared once data has been set to the register by the electronic volume register set command. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 10000001
data sheet s13368ej3v0ds00 34 m m m m pd16682 12.18.2 electronic volume register set command (second byte) when six bits of data are set to the electronic volume register by this command, the lcd drive voltage v lc1 is set to one of 64 possible voltage values. once this command has been input and the electronic volume register has been set, electronic volume mode is canceled. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v lc1 0 1 0 xx000000 smaller value xx000001 xx000010 xx111110 xx111111 larger value remark x: dont care figure 12 - - - - 3. sequence of electronic volume register set operations no ye s electronic volume mode set electronic volume register set cancel electronic volume mode changes completed? 12.19 static indicator (two-byte command) this command is used to control the indicator display for the static drive system. only this command can control the static indicator display, and it operates independently of other display control commands. one of the electrodes for the static indicators lcd driver is connected to the fr pin and the other is connected to the frs pin. we recommend that these status indicator electrodes be implemented in a pattern that is separate from the electrodes used for the dynamic drive. the lcd and the electrodes themselves may deteriorate if the patterns are laid out too close to each other. the static indicator on command is a two-byte command that is used in a pair with the static indicator register set command, so be sure to use both commands consecutively. (the static indicator off command is a one-byte command.)
data sheet s13368ej3v0ds00 35 m m m m pd16682 12.19.1 static indicator on/off when the static indicator on command is input, the static indicator register set command becomes valid. once the static indicator on command has been input, any command other than the static indicator register set command cannot be used. this restriction is cleared once data has been set to the register by the static indicator register set command. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 static indicator 0 1 0 10101100off 1on 12.19.2 static indicator register set this command sets data to the two-bit static indicator register and then sets the static indicator to blink mode. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 static indicator 0 1 0 xxxxxx0 0off 0 1 on (blinks at one- second interval) 1 0 on (blinks at half- second interval) 1 1 on (always on) figure 12 - - - - 4. sequence of static indicator register set operations no ye s static indicator on static indicator register set cancel static indicator mode changes completed? 12.20 power save (compound command) the current consumption can be greatly reduced by entering the power save status by inputting the display all on command while the display is in off mode. the power save (low power) mode includes two modes; sleep mode and standby mode. turning the static indicator off sets sleep mode and turning it on sets standby mode. during either sleep mode or standby mode, the display data is retained as it was before the power save function was activated. also, access to the display data ram from the mpu is possible during either mode. use the display all off command to cancel power save mode.
data sheet s13368ej3v0ds00 36 m m m m pd16682 figure 12 - - - - 5. power save static indicator off static indicator on power save (compound command) sleep mode static indicator on reset command standby mode power save off (display all off command) cancel sleep mode cancel standby mode power save off (display all off command) 12.20.1 sleep mode during this mode, all lcd operations are stopped and there is no access from the mpu, so current consumption can be reduced almost as low as the static current level. the internal status during sleep mode is as follows. (1) the oscillation circuit and lcd power supply circuit are stopped. (2) all lcd drive circuits are stopped and both segment and common driver outputs output at the v ss level. 12.20.2 standby mode during this mode, all duty lcd display system operations are stopped and only the static drive system for the indicators operate, which reduces the current consumption to the minimum amount needed for static drive. the internal status during standby mode is as follows. (1) the lcds power supply circuit is stopped. the oscillation circuit operates. (2) the duty drive systems lcd drive circuit is stopped and both segment and common driver outputs output at the v ss level. the static drive system operates. when a reset command is executed while in standby mode, it sets sleep mode. remarks 1. if you are using an external power supply, we recommend that you stop the external power supply circuits functions when activating the power save function. for example, if you are using an external divided resistor circuit to provide lcd drive voltage at different levels, we recommend that you add a circuit to cut the current flowing on the divided resistor circuit while the power save function is being activated. 2. the m pd16682 includes the /dof pin which is used to control blinking lcd displays is set to low level when activating the power save function. the output from /dof can be used to stop the external power supply circuit's function. 3. when the display has been set to off mode, executing the display all on command sets power save mode no matter which command is entered afterward.
data sheet s13368ej3v0ds00 37 m m m m pd16682 12.21 nop this command is used to set nop (non-operation) mode. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 11100011 12.22 test this command is used for ic testing. do not use this command. if you use it by mistake, either set the /res input low or use the reset command or nop command to cancel the test command setting. a0 e, /rd r,/w, /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1111xxxx remark x: dont care
data sheet s13368ej3v0ds00 38 m m m m pd16682 table 12 - - - - 1. list of m m m m pd16682 commands (1/2) command command code function a0 /rd /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display on/off 01010101110 1 sets lcds on/off status 0: off, 1: on display start line set 0 1 0 0 1 display start address sets display rams display start line address page address set 0 1 0 1 0 1 1 page address sets display rams page address column address set (high-order bits) 0 1 0 0 0 0 1 high-order column address sets high-order four bits of display rams column address column address set (low-order bits) 0 1 0 0 0 0 0 low-order column address sets low-order four bits display rams column address status read 0 0 1 0 status 0 0 0 0 read status information display data write 1 1 0 write data writes to display ram display data read 1 0 1 read data reads from display ram adc select 01010100000 1 sets correspondence of seg output to display ram address 0: normal, 1: inverted display normal/inverted 01010100110 1 sets normal/inverted direction of display display all on/off 01010100100 1 sets display all on 0: normal display, 1: all on lcd bias set 01010100010 1 sets the bias setting of the lcd drive voltage 0: 1/9 bias, 1: 1/7 bias read modify write 0 1 0 1 1 1 0 0 0 0 0 specifies incrementation of the column address during write: +1, during read: 0 end 0 1 0 1 1 1 0 1 1 1 0 cancels read modify write reset 01011100010sets an internal reset selects scan direction for com outputs 01011000 1 x x x x x x selects scan direction for com outputs 0: normal (forward), 1: inverted (reverse)
data sheet s13368ej3v0ds00 39 m m m m pd16682 table 12 - - - - 1. list of m m m m pd16682 commands (2/2) command command code function a0 /rd /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 power control set 0 1 0 0 0 1 0 1 operation mode selects operation mode of internal power supply sets v lc1 output voltage to electronic volume register 01000100resistance factor setting selects on-chip resistance factor for (ra/rb) electronic volume mode set 01010000001 electronic volume register set 0 1 0 x x electronic volume value sets v lc1 output voltage to electronic volume register static indicator on/off 01010101100 1 0: off, 1: on static indicator register set 0 1 0 x x x x x x mode sets on mode power save compound command for setting display off and all display on nop 0 1 0 1 1 1 0 0 0 1 1 command for non- operation mode test 0 1 0 1 1 1 1 x x x x command used for ic testing caution do not use this command. remark x: don't care
data sheet s13368ej3v0ds00 40 m m m m pd16682 13. access procedure 13.1 initialization setting example (from power application to display on) although a v ss level is output from the seg and com lcd drive output pins when power is applied to the ic, if there is electric charge remaining in the smoothing capacitor connected between the driver reference power supply pins (v lc1 to v lc5 ) and v ss , or if the dc/dc converter's booster voltage does not reach the prescribed booster potential or the levels of the reference power supplies (v lcn ) do not reach the prescribed voltages when power is applied, abnormalities such as a temporary screen blackout may occur when the display turns on. the following power application flow is recommend to avoid the occurrence of abnormal operation when the power is turned on. power supply between v dd /v dd2 and v ss on when /res pin in l state display on power supply stabilization reset state release (/res pin = h) initial settings state note1 user settings via command input (1) lcd bias set adc select common output status selection note2 note3 note4 user settings via command input (2) set on-chip resistance factor for v lc1 voltage regulator electronic volume note5 note6 user settings via command input (3) power control set note7 end of initial settings lcd display screen settings display start line set writing screen data, etc. note8 note9 be sure to allow at least 700 ms between power control set and display on (when the v lc1 to v lc5 smoothing capacitor is 0.22 m f or less). note10
data sheet s13368ej3v0ds00 41 m m m m pd16682 notes 1. see 11. reset circuit. 2. see 12.11 lcd bias set. 3. see 12.8 adc select (segment driver direction select). 4. see 12.15 common output status select. 5. see 12.17 set on-chip resistance factor for v lc1 voltage regulator. 6. see 12.18 electronic volume (two-byte command). 7. see 12.16 power control set. 8. see 12.2 display start line set. 9. see 12.1 display on/off. 10. this period changes depending on the panel characteristics and the capacitance of the booster/smoothing capacitor. it is recommended to determine this value after sufficient evaluation using the actual device. 13.2 example of power off when turning the power of the ic off in the normal operation state (liquid crystal display on, on-chip power supply circuits operating), because there is electric charge remaining in the power supply level smoothing capacitor connected between the driver reference power supply pins (v lc1 to v lc5 ) and v ss , power continues to be supplied to the lcd drive circuit and voltage may be applied to the lcd panel from the seg and com pins. at this time, the lcd panel may momentarily display data. moreover, because the visual quality of the lcd panel may be affected, be sure to turn off the power to the ic in the following sequence. normal operation state command input power save note1 reset (/res pin = l ) note2 power supply between v dd /v dd2 and v ss off notes1. see 12.20 power save (compound command). 2. application of a reset is optional.
data sheet s13368ej3v0ds00 42 m m m m pd16682 14. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit supply voltage v dd C0.3 to +6.0 v supply voltage 2 (4x boost) v dd2 - 0.3 to +3.75 v supply voltage 2 (3x boost) v dd2 - 0.3 to +5.0 v driver supply voltage v lcd - 0.3 to +15.0, v dd v lcd v driver reference supply input voltage v lc1 -v lc5 - 0.3 to v lcd +0.3 v logic system input voltage v in1 - 0.3 to v dd +0.3 v logic system output voltage v out1 - 0.3 to v dd +0.3 v logic system input/output voltage v i/o1 - 0.3 to v dd +0.3 v driver system input voltage v in2 - 0.3 to v lcd +0.3 v driver system output voltage v out2 - 0.3 to v lcd +0.3 v operating ambient temperature t a - 40 to +85 c storage temperature t stg - 55 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range parameter symbol min. typ. max. unit supply voltage v dd 1.8 4.5 v supply voltage 2 (4x boost) v dd2 2.4 3.0 v supply voltage 2 (3x boost) v dd2 2.4 4.0 v driver supply voltage v lcd 61012v logic system input voltage v in 0v dd v driver system input voltage v lc1 -v lc5 0v lcd v remarks 1. when using an external power supply, be sure to maintain these relations: v ss < v lc5 < v lc4 < v lc3 < v lc2 < v lc1 v lcd 2. maintain v dd v lcd when turning the power on or off. ?
data sheet s13368ej3v0ds00 43 m m m m pd16682 electrical characteristics (unless otherwise specified, t a = - - - - 40 to +85 c, v dd2 = 2.7 to 3.3 v, during 4x boost mode: v dd2 = 2.7 to 3.0 v, or during 3x boost mode: v dd2 = 2.7 to 4.0 v) parameter symbol condition min. typ. note max. unit high-level input voltage v ih 0.8 v dd v low-level input voltage v il 0.2 v dd v high-level input current i ih1 except for d 7 (si), d 6 (scl), and d 5 to d 0 1 m a low-level input current i il1 except for d 7 (si), d 6 (scl), and d 5 to d 0 - 1 m a high-level output voltage v oh i out = - 1.5 ma, except osc out v dd - 0.5 v low-level output voltage v ol i out = 4 ma, except osc out 0.5 v high-level leakage current i loh d 7 (si), d 6 (scl), and d 5 to d 0 v in/out = v dd 10 m a low-level leakage current i lol d 7 (si), d 6 (scl), and d 5 to d 0 v in/out = v ss - 10 m a common output on resistance r com v lcn ? com n, v lcd 3 3v dd2 , i lol = 50 m a2k w segment output on resistance r seg v lcn ? seg n, v lcd 3 3v dd2 , i lol = 50 m a4k w driver voltage (boost voltage) v lcd during 3x boost 2.7 v dd 3.0 v dd v during 4x boost 3.6 v dd 4.0 v dd v current consumption (normal mode) i dd11 f osc = 22 khz, all display off data output, v dd = v dd2 = 3.0 v during 3x boost mode, t a = 25 c 55 110 m a f osc = 22 khz, all display off data output, v dd = v dd2 = 3.0 v during 4x boost mode, t a = 25 c 78 135 m a current consumption (high-power mode) i dd12 f osc = 22 khz, all display off data output, v dd = v dd2 = 3.0 v during 3x boost mode, t a = 25 c 104 190 m a f osc = 22 khz, all display off data output, v dd = v dd2 = 3.0 v during 4x boost mode, t a = 25 c 153 230 m a current consumption (standby mode) i dd21 f osc = 22 khz, v dd = v dd2 = 3.0 v, t a = 25 c 715 m a current consumption (sleep mode) i dd22 all display off data output, v dd = v dd2 = 3.0 v 0.2 5 m a oscillation frequency f osc t a = 25 c, v dd = v dd2 = 3.0 v 10 % 17 22 25 khz note the typ. value is a reference value when t a = 25 c ?
data sheet s13368ej3v0ds00 44 m m m m pd16682 required timing conditions (unless otherwise specified, t a = - - - - 40 to +85 c) 80 series mpu t as8 t ah8 t cclw , t cclr t cyc8 t cchr , t cchw t dh8 t ds8 t acc8 t oh8 a0 /cs1 (cs2="1") /wr, /rd d 0 - d 7 (write) d 0 - d 7 (read) t f t r ( v dd = 2.7 to 4.5 v ) parameter symbol conditions min. typ. note max. unit address hold time t ah8 a0 0 ns address setup time t as8 a0 0 ns system cycle time t cyc8 300 ns control l pulse width (/wr) t cclw /wr 60 ns control l pulse width (/rd) t cclr /rd 120 ns control h pulse width (/wr) t cchw /wr 60 ns control h pulse width (/rd) t cchr /rd 60 ns data setup time t ds8 d 0 to d 7 40 ns data hold time t dh8 d 0 to d 7 15 ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 140 ns output disable time t oh8 d 0 to d 7 , c l = 100 pf 10 100 ns note the typ. value is a reference value when t a = 25 c
data sheet s13368ej3v0ds00 45 m m m m pd16682 ( v dd = 2.4 to 2.7 v) parameter symbol conditions min. typ. note max. unit address hold time t ah8 a0 0 ns address setup time t as8 a0 0 ns system cycle time t cyc8 1000 ns control l pulse width (/wr) t cclw /wr 120 ns control l pulse width (/rd) t cclr /rd 240 ns control h pulse width (/wr) t cchw /wr 120 ns control h pulse width (/rd) t cchr /rd 120 ns data setup time t ds8 d 0 to d 7 80 ns data hold time t dh8 d 0 to d 7 30 ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 280 ns output disable time t oh8 d 0 to d 7 , c l = 100 pf 10 200 ns note the typ. value is a reference value when t a = 25 c remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) < (t cyc8 Ct cclw Ct cchw ) or (t r + t f ) < (t cyc8 Ct cclw Ct cchr ). 2. all timing is rated based on 20 % or 80 % of v dd . 3. t cclw and t cclr are rated as the overlap time when /cs1 is at low level (cs2 = h) and /wr and /rd are also at low level.
data sheet s13368ej3v0ds00 46 m m m m pd16682 68 series mpu t as6 t ah6 t ewhr , t ewhw t cyc6 t ewlr , t ewlw t dh6 t ds6 t acc6 t oh6 a0 r,/w /cs1 (cs2="1") e d 0 - d 7 (write) d 0 - d 7 (read) t f t r ( v dd = 2.7 to 4.5 v ) parameter symbol conditions min. typ. note max. unit address hold time t ah6 a0 0 ns address setup time t as6 a0 0 ns system cycle time t cyc6 300 ns data setup time t ds6 d 0 to d 7 40 ns data hold time t dh6 d 0 to d 7 15 ns access time t acc6 d 0 to d 7 , c l = 100 pf 140 ns output disable time t oh6 d 0 to d 7 , c l = 100 pf 10 ns enable h pulse width read t ewhr e 120 ns write t ewhw e60ns enable l pulse width read t ewlr e60ns write t ewlw e60ns note the typ. value is a reference value when t a = 25 c
data sheet s13368ej3v0ds00 47 m m m m pd16682 ( v dd = 2.4 to 2.7 v ) parameter symbol conditions min. typ. note max. unit address hold time t ah6 a0, r,/w 0 ns address setup time t as6 a0, r,/w 0 ns system cycle time t cyc6 1000 ns data setup time t ds6 d 0 to d 7 80 ns data hold time t dh6 d 0 to d 7 30 ns access time t acc6 d 0 to d 7 , c l = 100 pf 280 ns output disable time t oh6 d 0 to d 7 , c l = 100 pf 10 ns enable h pulse width read t ewhr e 240 ns write t ewhw e 120 ns enable l pulse width read t ewlr e 120 ns write t ewlw e 120 ns note the typ. value is a reference value when t a = 25 c remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) (t cyc6 Ct ewlw Ct ewhw ) or (t r + t f ) (t cyc6 Ct ewlr Ct ewhr ). 2. all timing is rated based on 20 % or 80 % of v dd . 3. t ewhw and t ewlw are rated as the overlap time when /cs1 is at low level (cs2 = h) and e is at high level. 4. d 0 to d 7 change to output regardless of the state of the e signal when r,/w becomes h in the state of /cs1 = l, cs2 = h ( see 5.1.2. (2) 68 series parallel interface. ).
data sheet s13368ej3v0ds00 48 m m m m pd16682 serial interface t css t f t r t csh t sas t sah t slw t shw t scyc t sds t sdh /cs1 (cs2="1") a0 scl si ( v dd = 2.7 to 4.5 v ) parameter symbol conditions min. typ. note max. unit shift clock cycle t scyc scl 250 ns scl h pulse width t shw scl 100 ns scl l pulse width t slw scl 100 ns address setup time t sas a0 150 ns address hold time t sah a0 150 ns data setup time t sds si 100 ns data hold time t sdh si 100 ns cs-scl time t css /cs1,cs2 150 ns t csh /cs1,cs2 150 ns note the typ. value is a reference value when t a = 25 c
data sheet s13368ej3v0ds00 49 m m m m pd16682 ( v dd = 2.4 to 2.7 v ) parameter symbol conditions min. typ. note max. unit shift clock cycle t scyc scl 400 ns scl h pulse width t shw scl 150 ns scl l pulse width t slw scl 150 ns address setup time t sas a0 250 ns address hold time t sah a0 250 ns data setup time t sds si 150 ns data hold time t sdh si 150 ns cs-scl time t css /cs1,cs2 250 ns t csh /cs1,cs2 250 ns note the typ. value is a reference value when t a = 25 c remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. 2. all timing is rated based on 20 % or 80 % of v dd . common parameter symbol conditions min. typ. max. unit oscillation frequency f cl cl, when using external input, v dd = v dd2 = 3.0 v 10 %, t a = 25 c 17 22 25 khz remarks 1. the rise and fall times (t r and t f ) of input signals are rated at 15 ns or less. 2. the frame time can be determined using the following equation. 1 frame = 1/f osc or 1/f cl x 4 x duty value therefore, when f osc and f cl = 22 khz and the duty value is 1/65: 1 frame = 45.5 m s x 4 x 65 = 11.8 ms (approximately 84.6 khz)
data sheet s13368ej3v0ds00 50 m m m m pd16682 output timing for display output control t dfr cl (out) fr ( v dd = 2.7 to 4.5 v ) parameter symbol conditions min. typ. note max. unit fr delay time t dfr fr, c l = 50 pf 20 80 ns note the typ. value is a reference value when t a = 25 c ( v dd = 2.4 to 2.7 v ) parameter symbol conditions min. typ. note max. unit fr delay time t dfr fr, c l = 50 pf 50 200 ns note the typ. value is a reference value when t a = 25 c remark all timing is rated based on 20 % or 80 % of v dd .
data sheet s13368ej3v0ds00 51 m m m m pd16682 reset input timing t rw t r /res during reset reset completed internal status ( v dd = 2.7 to 4.5 v ) parameter symbol conditions min. typ. note max. unit reset time t r 1.0 m s reset l pulse width t rw /res 1.0 m s note the typ. value is a reference value when t a = 25 c ( v dd = 2.4 to 2.7 v ) parameter symbol conditions min. typ. note max. unit reset time t r 1.5 m s reset l pulse width t rw /res 1.5 m s note the typ. value is a reference value when t a = 25 c remark all timing is rated based on 20 % or 80 % of v dd .
data sheet s13368ej3v0ds00 52 m m m m pd16682 15. standard tcp package drawing ( m m m m pd16682n-xxx-051)(1/3)
data sheet s13368ej3v0ds00 53 m m m m pd16682 standard tcp package drawing ( m m m m pd16682n-xxx-051)(2/3) detail of hole detail of hole 0.2 2 - r0.5 cu hole 2 - r0.8 cu 2 - r0.6 pi hole f 1.2 pi hole cu hole f 1.6 cu f 1 detail of alignment mark detail of alignment mark 0.05 0.6 8.8 from p.c. 0.3 31.175 mark to mark 0.05 tcp tape winding method output lead tape pullout direction copper pattern on back side of tape winding direction
data sheet s13368ej3v0ds00 54 m m m m pd16682 standard tcp package drawing ( m m m m pd16682n-xxx-051)(3/3) pin configuration nc nc nc coms com 63 com 62 com 61 com 60 com 27 com 28 com 29 com 30 com 31 nc nc nc nc frs fr cl /dof test out v ss ' /cs1 cs2 v dd ' /res a0 v ss ' /wr, r,/w /rd,e v dd ' d 0 d 1 d 2 d 3 d 4 d 5 d 6 ,scl d 7 ,si v dd v dd2 v lcd v ss c 1 c 1 c 2 c 2 c 3 c 3 v ss ' v dd ' v rs v r v lc1 v lc2 v lc3 v lc4 v lc5 v ss ' test1 test2 test3 test4 test5 v dd ' m,/s cls v ss ' c86 p,/s v dd ' hpm v ss ' irs v dd ' nc no.1 no.2 no.3 no.4 no.5 no.6 no.7 no.8 no.9 no.10 no.11 no.12 no.13 no.14 no.15 no.16 no.17 no.18 no.19 no.20 no.21 no.22 no.23 no.24 no.25 no.26 no.27 no.28 no.29 no.30 no.31 no.32 no.33 no.34 no.35 no.36 no.37 no.38 no.39 no.40 no.41 no.42 no.43 no.44 no.45 no.46 no.47 no.48 no.49 no.50 no.51 no.52 no.53 no.54 no.55 no.56 no.57 no.58 no.59 no.60 no.61 die : face up + - - - + + no.1 no.2 no.3 no.4 no.5 no.6 no.7 no.8 no.197 no.198 no.199 no.200 no.201 no.202 no.203 no.204
data sheet s13368ej3v0ds00 55 m m m m pd16682 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16682 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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